We're hiring

We are hiring an AI Silicon Architect specializing in memory systems for real-time AI inference pipelines. You will architect low-latency memory protocols and data-movement paths across heterogeneous compute blocks, caches, and memory interfaces. We need a self-motivated problem solver who thinks unconventionally to solve extreme physical and architectural constraints for next-generation Physical AI systems.

Key Qualifications

• Ph.D. in Computer Architecture, EE, or CE or an exceptional Master's/Bachelor's degree, with a proven track record of shipping hardware, or a tenured/tenure-track professor seeking a sabbatical placement
• Strong understanding of memory interfaces (DDR, LPDDR, HBM) and their integration with memory controllers, PHYs, high-speed caches, and scratchpads
• Proven familiarity with hardware execution patterns, deterministic latency requirements, and data-movement bottlenecks in real-time systems
• Hands-on experience with C++/Python performance modeling and cycle-accurate simulators, combined with SystemVerilog RTL development and proficiency in Synopsys or Cadence EDA tools across synthesis and physical implementation
• Publications in top architecture venues (e.g., ISCA, MICRO, HPCA, ASPLOS, or SC) are preferred

Key Responsibilities

• Collaborate closely with physical domain, silicon, and compiler teams to co-design and architect high-throughput memory subsystems for next-generation Physical AI platforms
• Clearly articulate product vision, hardware roadmaps, and technical specifications to IP suppliers, foundry partners, strategic customers, and venture investors
• Drive architectural trade-offs independently in a fast-paced, high-ownership environment from concept down to execution

We are hiring an AI Package Architect with deep expertise in 2.5D/3D integration, chiplets, CoWoS, EMIB, and FO-WLP. We need an unconventional, high-ownership problem solver to architect next-generation multi-die packages and push the boundaries of silicon packaging.

Key Qualifications

• Ph.D. in EE, ME, Materials Science, or an exceptional Master's/Bachelor's degree, with a proven track record of shipping hardware, or a tenured/tenure-track professor seeking a sabbatical placement
• Deep fundamentals in advanced semiconductor packaging technologies (2.5D/3D integration, System-on-Wafer, substrate design, high-density interconnects, thermal/mechanical modeling)
• Strong understanding of memory physical interfaces (HBM, LPDDR, DDR) and their integration with memory controllers, PHYs, and high-speed interconnects within a package
• Proficiency with industry-standard package layout tools, including Cadence APD+/Integrity 3D-IC, Synopsys 3DIC Compiler, or Siemens Xpedition/Calibre 3DSTACK
• A strong publication record in top packaging journals and conferences (ECTC, EPTC, SEMICON, ISSCC) is a plus

Key Responsibilities

• Partner closely with silicon, thermal, and memory teams to architect packages for Physical AI edge platforms
• Drive end-to-end packaging execution across physical domains from initial architectural concepts down to vendor selection and manufacturing bring-up
• Interface directly with packaging foundry, substrate suppliers, IP vendors, and venture partners to evaluate emerging packaging roadmaps and drive custom co-development
• Serve as an independent, self-directed researcher and architect unafraid to challenge conventional designs to solve system bottlenecks

We are hiring an AI Thermal Architect with deep domain expertise in advanced thermal management, heat transfer, and thermal-fluid systems for microelectronics. Our ideal candidate is a self-motivated, highly driven researcher who thinks unconventionally to solve high-density thermal constraints for next-generation Physical AI hardware.

Key Qualifications

• Ph.D. in EE, ME, Materials Science, or an exceptional Master's/Bachelor's degree, with a proven track record, or a tenured/tenure-track professor seeking a sabbatical placement
• Deep fundamentals in microelectronics cooling, two-phase heat transfer, vapor chambers, liquid cooling/cold plates, microchannel flows, and thermal interface materials
• Strong understanding of thermal interaction with advanced packaging (2.5D/3D ICs, Chiplets, HBM), board layout, structural heatsinks, and compact form-factor enclosures
• Proficiency with industry-standard CFD and thermal modeling tools (e.g., Ansys Icepak, Ansys Fluent, COMSOL, SolidWorks Flow Simulation, etc.)
• A strong publication record or research contributions in top thermal-fluid journals and conferences (e.g., ECTC, SEMI-THERM, ITherm, TMSS) is a plus
• General understanding of AI inference pipelines and hardware system design is a plus

Key Responsibilities

• Partner closely with other teams to architect thermal management systems for dense Physical AI edge compute platforms
• Define electro-thermal trade-off models with power density and cooling overhead to optimize thermal-fluid performance under real-world workload constraints
• Drive thermal execution from early-stage CFD simulation and architecture concepts down to thermal solution, prototype validation, and manufacturing bring-up
• Interface directly with cooling component vendors, heatsink manufacturers, liquid-cooling suppliers, and strategic partners to evaluate emerging cooling technologies and drive custom thermal hardware co-development